Date Posted: 03/09/2026
Hiring Organization: Rose International
Position Number: 498078
Industry: Social Media
Job Title: Optical Engineer
Job Location: Redmond, WA, USA, 98052
Work Model: Onsite
Shift: 1st shift, onsite
Employment Type: Temporary
FT/PT: Full-Time
Estimated Duration (In months): 13
Min Hourly Rate($): 70.00
Max Hourly Rate($): 80.00
Must Have Skills/Attributes: Circuitry, Electrical Engineer, MATLAB, Optics development, Python
Experience Desired: PIC Design & Simulation (3+ yrs); Photonic Modeling Tools (3+ yrs); PIC Layout & Tapeout (3+ yrs)
Required Minimum Education: Master’s Degree
Preferred Education: Ph.D / Doctorate
**C2C is not available**
Job Description
True Job Title: Optical Engineer, Photonic Integrated Circuit (PIC) Design & Analysis
EDUCATION
• MS or Ph.D. degree in Electrical Engineering, Optical Sciences, Physics, or a closely related field.
MUST-HAVE SKILLS
1. PIC Design & Simulation: 3+ years designing, simulating, and laying out photonic integrated circuits (PICs) for visible/IR wavelengths.
2. Photonic Modeling Tools: Proficiency with tools like Lumerical, Ansys Photonics, Synopsys RSoft, or COMSOL for device/circuit analysis.
3. PIC Layout & Tapeout: Experience with layout tools (KLayout, Cadence Virtuoso, gdsfactory), GDSII generation, and supporting tapeouts at commercial foundries.
REQUIRED SKILLS
• Minimum years of total experience: 5 years
• 3+ years of hands-on experience in the design, simulation, and layout of PICs for visible or IR wavelengths on platforms such as Si, SiN, LiNbO, or BTO.
• 3+ years of experience utilizing photonic device simulation and electromagnetic modeling tools for both component and circuit-level analysis (e.g., Lumerical FDTD/MODE/DEVICE, Ansys Photonics, Synopsys RSoft, or COMSOL Multiphysics).
• 2+ years of experience with PIC layout tools and GDSII generation (e.g., KLayout, Cadence Virtuoso, gdsfactory, or equivalent), including familiarity with foundry PDK integration and design rule verification.
• 2+ years of experience with scientific programming (e.g., Python or MATLAB) for scripting, design automation, and analysis.
• 1+ years of experience supporting or executing PIC tapeouts at a commercial semiconductor foundry, including an understanding of fabrication process constraints (e.g., propagation losses, sidewall roughness, etch non-idealities).
NICE-TO-HAVE SKILLS
1. Active PIC Design & Validation: Experience in active PIC design, fabrication, and validation, especially for visible wavelengths.
2. Device Characterization: Skills in optical/electro-optic measurements, fiber optics, free-space optics, and PIC packaging.
3. Statistical Modeling & Sensitivity Analysis: Experience in design space exploration, yield modeling, and incorporating fabrication constraints.
PREFERRED SKILLS
• 3+ years experience in active PIC design, fabrication, and validation, particularly for visible wavelengths on LiNbO or BTO platforms.
• 3+ years of experience in design space exploration, sensitivity analysis, and statistical performance/yield modeling for photonic circuits.
• 3+ years of experience with one or more major photonic simulation tool suites (e.g., Lumerical, Synopsys, COMSOL, or equivalent).
• 2+ years of experience utilizing photonic circuit-level simulation tools (e.g., Lumerical Interconnect, Synopsys OptSim, or VPIphotonics) for system-level performance evaluation.
• 2+ years of experience in photonic device characterization and test, including both optical and electro-optic measurements.
• 1+ years experience with fiber optics, free-space optics, PIC packaging, and comprehensive device characterization.
• 1+ years experience with semiconductor fabrication processes and a deep understanding of process-induced performance limitations, such as optical losses, sidewall roughness, and process variability.
• Demonstrated ability to directly incorporate fabrication constraints into PIC designs (e.g., optimizing minimum feature sizes and bend radii, implementing effective tapering strategies, and using layout techniques to mitigate scattering and coupling losses).
• Former Hi-Tech company experience such as Google, Microsoft, Amazon, etc. is considered a plus
SUMMARY
• We are seeking a passionate Optical Engineer to join our research and development team.
• This role focuses on delivering state-of-the-art near-to-eye display system technologies.
• The ideal candidate will have expertise in novel integrated photonics device design and metrology, gained through a Ph.D. or industry experience.
RESPONSIBILITIES
• Design and develop complete Photonic Integrated Circuits (PICs), from fundamental component blocks to full-circuit implementations, with a strong emphasis on active device integration.
• Generate, verify, and prepare fabrication-ready layout files, ensuring compliance with foundry Process Design Kits (PDKs) for external fabrication.
• Conduct systematic design analysis, including optimization and parametric studies, to guide design decisions.
• Support the entire design-to-fabrication pipeline, from initial concept through tapeout, coordinating closely with cross-functional teams and external partners.
• Collaborate with program leadership, Technical Program Managers (TPMs), and researchers on PIC designs that align with overall program objectives.
INTERVIEW PROCESS
• 1 round, panel interview with 2-3 interviewers
• Focus: Q&A covering diffractive optics, hands-on experimental experience, and discussion of the candidate’s PhD work
Pursuant to the California Fair Chance Act, Los Angeles County Fair Chance Ordinance for Employers, Los Angeles Fair Chance Initiative for Hiring Ordinance, and San Francisco Fair Chance Ordinance, qualified applicants will be considered for assignment with arrest and conviction records. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness, meet client expectations, standards, and accompanying requirements, and safeguard business operations and company reputation.
- **Only those lawfully authorized to work in the designated country associated with the position will be considered.**
- **Please note that all Position start dates and duration are estimates and may be reduced or lengthened based upon a client’s business needs and requirements.**
Benefits:
For information and details on employment benefits offered with this position, please visit here. Should you have any questions/concerns, please contact our HR Department via our secure website.
California Pay Equity:
For information and details on pay equity laws in California, please visit the State of California Department of Industrial Relations' website here.
Rose International is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender (expression or identity), national origin, arrest and conviction records, disability, veteran status or any other characteristic protected by law. Positions located in San Francisco and Los Angeles, California will be administered in accordance with their respective Fair Chance Ordinances.
If you need assistance in completing this application, or during any phase of the application, interview, hiring, or employment process, whether due to a disability or otherwise, please contact our HR Department.
Rose International has an official agreement (ID #132522), effective June 30, 2008, with the U.S. Department of Homeland Security, U.S. Citizenship and Immigration Services, Employment Verification Program (E-Verify). (Posting required by OCGA 13/10-91.).
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